This application relies for priority upon Korean Patent Application No. 2002-07294, filed on Feb. 8, 2002, the contents of which are herein incorporated by reference in their entirety.
1. Field of the Invention
The present invention relates to methods for fabricating semiconductor devices, and more particularly to methods for forming capacitors of a cylinder shape using a molding pattern.
2. Background of the Invention
A memory semiconductor device includes a structure for storing information in each unit cell. In particular, dynamic read access memory (DRAM), which is a widely used semiconductor memory device, uses a capacitor for storing the information. Meanwhile, as semiconductor devices continue to become more highly integrated, the available capacitor area per unit cell area decreases. However, at the same time, in order to ensure stable operation in the DRAM, it is necessary to secure sufficient capacitance in the DRAM cell capacitor.
As is known to those skilled in the art, the capacitance of a capacitor is directly proportional to a dielectric constant of a dielectric layer and to the respective areas of the capacitor electrodes, and is inversely proportional to the distance between capacitor electrodes. Thus, to maximize the capacitance of the capacitor, it is required to increase the respective areas of the capacitor electrodes, to decrease the distance between the capacitor electrodes, and to use a material layer having a high dielectric constant for the dielectric layer of the capacitor.
In general, for increasing the area of the capacitor electrode, the lower electrode of the capacitor is formed into a cylinder shape. Meanwhile, techniques for decreasing the distance between the capacitor electrodes has reached technical limits due to a problem with leakage current. Thus, a technique of using a material layer with a high dielectric constant has recently attracted attention as a method for increasing the capacitance of the dielectric layer of the capacitor.
When a high dielectric constant material is used for the capacitor dielectric layer, ruthenium is preferably used as an electrode material. However, because ruthenium exhibits a poor adhesion with nitride layers or oxide layers, the lower cylindrical electrode may sink while the lower electrode is formed.
FIGS. 1 and 2 are cross-sectional views illustrating a conventional method for forming a cylindrical capacitor and various problems associated therewith.
Referring to FIG. 1, an interlayer dielectric (ILD) 10 is formed on a semiconductor substrate and a contact plug 15 is then formed to penetrate the ILD 10. A supporting layer, an etch stop layer, and a molding layer are sequentially formed on the resulting surface of the semiconductor substrate including the contact plug 15. The molding layer, the etch stop layer, and the supporting layer are successively patterned to form a molding pattern 30, an etch stop pattern 25, and a supporting pattern 20, which have an opening exposing the contact plug 15.
A lower electrode layer (not shown) and a sacrificial layer (not shown) are formed on the resultant structure where the supporting pattern 20 is formed. Thereafter, the sacrificial layer and the lower electrode layer are planarizingly etched until the molding pattern 30 is exposed, thereby forming a sacrificial pattern 40 and a lower electrode 35.
The molding pattern 30 and the supporting pattern 20 are typically formed of a silicon oxide layer, and the etch stop pattern 25 is formed of a silicon nitride layer. Also, the lower electrode 35 is composed of a material of the platinum group such as ruthenium, and the sacrificial pattern 40 is composed of an SOG material.
Referring to FIG. 2, the molding pattern 30 and the sacrificial pattern 40 are removed by a wet etching process using an etch recipe for etching an oxide layer. However, as mentioned above, adhesion of ruthenium with the silicon nitride layer is poor. Thus, while the molding pattern 30 is removed, etchant may penetrate through a space formed between the etch stop pattern 25 and the lower electrode 35. As a result, along with the molding pattern 30, the supporting pattern 20 composed of a silicon oxide layer is also etched to form an undercut region 99 under the etch stop pattern 25. The etchant may penetrate through an interface between the molding pattern 30 and the lower electrode 35, due to a poor adhesion between the ruthenium and the silicon oxide layer. The penetration of the etchant may also cause the formation of the undercut region 99.
Because of the undercut region 99, the supporting pattern 20 is not able to structurally support the lower electrode 35. As a result, the lower electrode 35 may sink or fall down during a subsequent process, such as a subsequent cleaning process, and this can have catastrophic results. In addition, the undercut region 99 is not filled during a subsequent process due to the etch stop pattern 25 covered thereon and may remain as a void.
It is therefore a feature of the present invention to provide a method for forming a capacitor of a semiconductor device capable of overcoming the above mentioned limitations of the conventional approaches.
In accordance with an aspect of the present invention, there is provided a method for forming a capacitor of a semiconductor device comprising forming an adhesive spacer having a good adhesion with an etch stop pattern, so as to prevent an etchant for removing a molding pattern from penetrating into a supporting pattern. The method comprises forming a contact plug penetrating an interlayer dielectric (ILD) on a semiconductor substrate. A supporting layer, an etch stop layer, and a molding layer are sequentially formed on the semiconductor substrate where the contact plug is formed. The molding layer is then patterned to form a molding pattern. At this time, the molding pattern has an opening that exposes the etch stop layer over the contact plug. Thereafter, an adhesive spacer is formed on sidewalls of the opening. The etch stop layer and the supporting layer, which are exposed through the opening where the adhesive spacer is formed, are successively patterned. Thus, an etch stop pattern and a supporting pattern are formed to expose the contact plug. A lower electrode is formed to cover a hole region surrounded by sidewalls of the adhesive spacer, the etch stop pattern and the supporting pattern. The molding pattern is then removed to expose an outer wall of the adhesive spacer. Next, after removing the exposed adhesive spacer, a dielectric pattern and an upper electrode are formed to cover an exposed surface of the lower electrode.
At this time, the supporting layer is formed of a silicon oxide layer, and the etch stop layer is formed of a silicon nitride layer (Si3N4) or a tantalum oxide layer (Ta2O5). The molding layer is preferably composed of a silicon oxide layer or an SOG material.
Also, the adhesive spacer is composed of a material having beneficial adhesion and an etch selectivity with respect to the etch stop pattern and the lower electrode. For this, the adhesive spacer is preferably formed of a titanium nitride layer (TiN). In addition, forming the adhesive spacer preferably comprises forming an adhesive layer on an entire surface of the semiconductor substrate including the molding pattern, and then anisotropically etching the adhesive layer to expose top surfaces of the molding pattern and the contact plug.
The etch stop pattern and the supporting pattern are preferably formed by successively anisotropic-etching the etch stop layer and the supporting layer by using the adhesive spacer and the molding pattern as an etch mask.
The lower electrode is preferably composed of one of the platinum group, such as ruthenium, rhodium, palladium, osmium, iridium, or platinum. Forming the lower electrode comprises sequentially forming a lower electrode layer and a sacrificial layer on the resultant structure where the supporting pattern is formed, and then etching the sacrificial layer and the lower electrode layer until a top surface of the molding pattern is exposed. After forming the lower electrode, a thermal process may be further applied to the lower electrode in a hydrogen ambient.
Removing the molding pattern adopts an isotropic etch process using an etch recipe having an etch selectivity with respect to the adhesive spacer and the lower electrode. The sacrificial layer is preferably removed together during the process of removing the molding pattern.
Removing the adhesive spacer adopts an isotropic etch process using an etch recipe having an etch selectivity with respect to the lower electrode and the etch stop pattern. At this time, an etchant is preferably a solution mixture of sulfuric acid (H2SO4) and hydrogen peroxide (H2O2).
The dielectric layer is preferably formed of a tantalum oxide layer. After forming the dielectric layer and the upper electrode layer, a thermal process may be further applied to the dielectric layer and the upper electrode layer.